In general, an active matrix liquid crystal display device having a thin film transistor comprises a plurality of scanning lines (gate lines) and a plurality of signal lines (data lines) disposed in the horizontal and the vertical direction respectively, a thin film transistor (TFT) as a non-linear element at each of the intersections of the scanning and signal lines, and one transparent insulating substrate having a transparent display electrode connected to each thin film transistor. The other transparent insulating substrate has a color filter, a common electrode, and a reflecting metal black matrix. Liquid crystal materials are maintained between these two transparent insulating substrates. A light source radiates light from the back of one transparent insulating substrate toward the other transparent insulating substrate. A driver device applies scanning voltage to said scanning lines, and another driver device applies signal voltage to said signal lines. The transparent display electrode and the TFT are formed for each liquid crystal cell which forms a pixel element, and optical characteristics for each pixel are modulated according to the magnitude of the scanning and signal voltage.
A TFT has been recently proposed in which a channel protective insulating layer is formed on a semiconductor layer serving as a channel so as to prevent the semiconductor layer from being etched. FIG. 1A shows an enlarged plan view and FIG. 1B shows a sectional view of a TFT structure made by the inventors of the present invention. A thin film transistor 1 includes a light shielding gate electrode 3 connected to said scanning lines and formed on an insulating substrate 2 such as a glass substrate, a gate insulator film 4 formed to cover the gate electrode 3, a semiconductor layer 5 formed on the gate insulator film 4 for operating as a channel, a channel protective insulator film 6 formed on a part of the semiconductor layer 5, and a source electrode 7 and a drain electrode 8 connected to said signal lines and electrically contacting said semiconductor layer 5. The source electrode 7 and the drain electrode 8 are light shielding metal layers such as aluminum and may also have an N+amorphous silicon layer 9 so as to maintain good ohmic contact with the semiconductor layer 5. The transistor uses as materials of the semiconductor layer 5 intrinsic amorphous silicon (a-Si), polycrystal silicon (p-Si) and the like. The channel protective insulator film 6 which determines the length of the channel is needed to prevent the thin semiconductor layer 5 from being etched and is formed by a nitride film and the like. It is known that leakage current is caused in the intrinsic amorphous silicon semiconductor layer 5 due to incident light from a surface, which is emitted from a light source, passes through liquid crystal materials, reflects on the inner surface of the other transparent insulating substrate, and passes through a transparent nitride film. This is because holes and electrons are generated when light is projected into an intrinsic amorphous silicon layer. This leakage current causes no problem when the TFT is turned on. However, when the leakage current flows between source and drain electrodes when the TFT is turned off, the voltage applied to the liquid crystal is changed and consequently display quality is remarkably degraded.
Accordingly, the inventors of the present invention conducted the following experiment to determine which path in the TFT the leak current flows through. First, the TFT was placed in a dark box and current during the turn off period of the TFT (Ioff) was measured. This OFF-state current is about 10 .sup.12 A in a TFT of normal size. Then, the OFF-state current between source and drain electrodes was measured by moving a narrow light stripe from a position P1 to a position P10 in order as shown in FIGS. 2A and 2B FIG. 2B shows the result of the experiment. The abscissa shows positions and the ordinate shows OFF-state current. The value of the OFF-state current Ioff is represented by a logarithmic value. Further, the value of the OFF-state current is represented by an arbitrary scale since it depends on the intensity of projected light, and Ioff=0 is about 10.sup.-12 A and Ioff=1 is about 10.sup.-11 A. The OFF-state current increased by about one digit (order of magnitude) at a position P6, while the OFF-state current at positions P1 and P9 indicated small values.
In the position P1, since an overlap margin of a mask for forming source and gate electrodes during the manufacturing process is needed, the source electrode 7 and the drain electrode 8 are extended to cover the channel protective insulator film 6 by a distance of about 2 to 3 .mu.m, which is longer than a hole-electron recombination distance, that is, about 1 .mu.m. Therefore, if a light stripe is positioned at the position P1, holes and electrons are not generated in the semiconductor area in which light is blocked by the source electrode 7 and drain electrode 8, and holes and electrons are generated in a semiconductor area in which light is not blocked by the source electrode 7 and drain electrode 8. Since these latter holes and electrons are recombined and decay before reaching the source electrode 7 or the drain electrode 8, the leakage current between the source electrode 7 and the drain electrode 8 is very low. This very low current is dark current and has no effect on the operation of the TFT.
In the position P9, since the light stripe is positioned away from the edges of the source electrode 7 and the drain electrode 8 by a distance which is longer than a distance for recombining holes and electrons, even if holes and electrons are generated in the semiconductor area in which the light stripe is projected, these holes and electrons recombine and decay before reaching the source electrode 7 and the drain electrode 8, and consequently the leakage current between the source electrode 7 and the drain electrode 8 is very low. In the position P6, the edges of the source electrode 7 and the drain electrode 8 overlap the edges of the semiconductor layer 5. If a light stripe is positioned at position P6 within a hole-electron recombination distance, holes and electrons which are generated within semiconductor area between Y1 and Y2 and between Y3 and Y4 (FIG. 1A), in which light is not blocked by the source electrode 7, the drain electrode 8 and the channel protective insulator film 6, immediately reach the source electrode 7 and the drain electrode 8. Further, since holes and electrons generated due to incident light exist between Y2 and Y3, a path for leakage current is formed between the drain electrode 8 and the source electrode 7. Thus, the inventors of the present invention established that holes and electrons, which are generated in an area of the semiconductor layer 5 within a hole-electron recombination distance from the edges of a source electrode and those of a drain electrode overlapping the semiconductor layer 5, respectively, and which reach the source and drain electrodes, contribute to a high leakage current caused during the turn off period of the TFT. A first prior art technique for preventing leakage current is to interrupt the projection of light at the overall semiconductor layer. For example, Japanese Published Unexamined Patent Application (PUPA) No. 59-117267 discloses that an extra light shielding film is formed above a channel region between source and drain electrodes of a TFT and has a larger area than the region. However, this has a defect in that yield is decreased, since an additional process for forming the light shielding film is needed and the number of processes is increased.
A second prior art technique is disclosed in PUPA No. 3-85767, in which an extra thick semiconductor layer for recombining and decaying holes and electrons generated due to incident light is provided between a semiconductor layer serving as a channel of a TFT and source and drain electrodes. When the TFT is turned on, a large quantity of electrons is injected into the extra semiconductor layer from the source electrode to form a conducting path. This also causes the number of processes to increase and yield to decrease.